1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly to a layout method of a nonvolatile semiconductor memory device manufactured in a CMOS process.
2. Description of the Related Art
Nonvolatile semiconductor memories are used in various systems. The combination of the nonvolatile memory and a logic LSI on the same semiconductor substrate can achieve lower process cost and miniaturization. However, a method of forming and combining a nonvolatile memory and a logic LSI on different chips or a method of changing a standard CMOS process to combine a nonvolatile memory and a logic LSI on the same chip are conventionally used due to a difference in manufacturing process, resulting in high process cost and complexity.
As a solution of this problem, a nonvolatile memory is known which is readily manufactured by a CMOS process, forms a floating gate by using the gates of an NMOS transistor and a PMOS transistor, and uses the diffusion region of the PMOS transistor as a control gate. See Japanese Unexamined Patent Publication No. 6-334190 and Japanese Unexamined Patent Publication No. 6-53521, for example.
Further, a nonvolatile memory is available in which a first PMOS diffusion region is used as a control gate for writing and reading and a second PMOS diffusion region is used for erasing. See Richard J. McPartland and Ranbir Singh, “1.25 Volt, Low Cost, Embedded FLASH Memory for Low Density Applications” 2000 Symposium on VLSI Circuits Digest of Technical Papers 1 2.2, for example.
Regarding nonvolatile semiconductor memories manufactured by a CMOS process, the above documents disclose a cell structure and a circuit technique for incorporating the structure as an array but do not disclose any layout method for reducing the area of a cell array in the array arrangement of memory cells.
Such nonvolatile semiconductor memories are currently used in small capacity systems. A future capacity increase will make an area of a cell array an important factor in consideration of cost.
The present invention relates to a nonvolatile memory manufactured by a CMOS process and particularly proposes a nonvolatile semiconductor memory device with a layout method for reducing the area of a cell array in the array arrangement of a memory cell composed of a single NMOS transistor and a single PMOS transistor and a memory cell which has two different control gates and is composed of a single NMOS transistor and two PMOS transistors.